1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and more particularly to the improvement of a channel region of a memory cell.
2. Description of the Related Art
FIG. 1 is a cross sectional view of a general memory cell which is used in an electrically data programmable and erasable non-volatile semiconductor memory device, and FIG. 2 is a diagram showing the impurity profile along the A--A line in FIG. 1.
As shown in FIG. 1, a P-type silicon substrate 1 containing boron (B) of approximately 10.sup.18 cm.sup.-3 is used and an N-type source diffused layer 2 and an N-type drain diffused layer 3 are separately formed in the substrate 1. A portion of the substrate 1 which lies between the diffused layers 2 and 3 is defined as a P-type channel region 4. A first gate insulation film 5 of silicon dioxide is formed on the channel region 4 and a floating gate 6 of polysilicon is formed on the first gate insulation film 5. A second gate insulation film 7 of silicon dioxide is formed on the floating gate 6 and a control gate 8 of polysilicon is formed on the second gate insulation film 7.
The impurity profile in the channel region of the memory cell with the above structure is shown in FIG. 2.
The line I in FIG. 2 indicates the boron profile. As indicated by the line I, the channel region has a P-type which is the same conductivity type as that of the substrate 1 and the concentration thereof is approximately 10.sup.18 cm.sup.-3 and substantially uniform in the depth direction of the channel region 4.
Next, the operation of the memory cell shown in FIG. 1, particularly, the readout operation thereof is explained below.
FIG. 3A is a cross sectional view for illustrating the readout operation effected when a large amount of electrons are present in the floating gate, and FIG. 3B is a cross sectional view for illustrating the readout operation effected when only a small amount of electrons are present in the floating gate.
First, as shown in FIG. 3A, when a large amount of electrons e are present in the floating gate 6, the threshold voltage of the cell is increased. Therefore, even if a readout voltage of 5 V (VCC) is applied to the control gate 8, an inverted layer is not formed in the channel region 4. As a result, the cell is kept in the non-conductive state.
On the other hand, as shown in FIG. 3B, when only a small amount of electrons e are present in the floating gate 6, the threshold voltage of the cell becomes lower than that of a case shown in FIG. 3A. Therefore, when a readout voltage of 5 V is applied to the control gate 8, an inverted layer 40 is formed in the channel region 4. As a result, the cell is set into the conductive state. At this time, in the conventional memory cell, the inverted layer 40 is formed in contact with the surface 9 of the substrate 1 in the channel region 4.
In this specification, the storage state of the memory cell is defined such that "0" level data is stored when a large amount of electrons e are present in the floating gate 6 and the threshold voltage of the memory cell is high and "1" level data is stored when only a small amount of electrons e are present in the floating gate 6 and the threshold voltage of the memory cell is low.
In the memory cell shown in FIG. 1, the electrically data erasing and writing operations are effected. Particularly, at the time of data writing, a programming voltage (VPP) is applied to the control gate 8 and a voltage is applied between the source and the drain to cause a current to flow in the inverted layer 40, which generates channel hot electrons and injects the thus generated channel hot electrons into the floating gate 6. This operation is effected each time data is re-written and holes and electrons pass through the first gate insulation film 5 at each time of the operation. If holes and electrons pass through the first gate insulation film 5, an interface state 41 is formed in the interface between the surface 9 of the substrate 1 in the channel region 4 and the first gate insulation film 5. The amount of the interface state is gradually increased each time data is re-written. The interface state reduces a cell current, that is, a current flowing in the channel region 4 in the readout operation. Therefore, as the amount of the interface state is increased, the cell current is gradually reduced. Finally, almost no cell current is caused to flow, making it impossible to read out "1" level data.
As described above, in the memory cell shown in FIG. 1, it is difficult to stably readout data for a long period of time because of its structure. That is, the durability of the memory cell is not excellent.
Further, as one of the factors for determining the performance of the memory cell, the operation speed is considered. Particularly, the data writing speed is important.
However, in the memory cell shown in FIG. 1, an increase in the data writing speed is limited because of its structure. That is, the writing speed is low.